The fabrication of advanced integrated circuits requires the formation of a large number of circuit elements in a given chip area according to a specified circuit layout. Field effect transistors (NMOS and PMOS transistors) represent one important type of circuit elements that substantially determine performance of the integrated circuits. During the fabrication of complex integrated circuits using, for instance, MOS technology, millions of transistors, e.g., NMOS transistors and/or PMOS transistors are formed on a substrate including a crystalline semiconductor layer. A field effect transistor, irrespective of whether an NMOS transistor or a PMOS transistor is considered, typically comprises so-called PN junctions that are formed by an interface of highly doped regions, referred to as drain and source regions, with a slightly doped or non-doped region, such as a channel region, disposed between the highly doped regions source/drain regions. Improvement of the electrical performance characteristics of semiconductor devices, such as transistors, and the overall performance capabilities of integrated circuit devices that incorporate such devices is constantly sought.
Ion implantation is a technique that is employed in many technical fields to implant dopant ions into a substrate so as to alter the characteristics of the substrate or of a specified portion thereof. For example, the rapid development of advanced devices in the semiconductor industry is based on, among other things, the ability to generate highly complex dopant profiles within tiny regions of a semiconductor substrate by performing advanced implantation techniques through a masking.
When implanting specified ions into a substrate, the desired lateral implant profile may be readily obtained by providing correspondingly adapted implantation masks. A desired vertical implant profile may be achieved by, among other things, controlling the acceleration energy of the ions during the implantation process such that the majority of the ions at positioned at a desired depth in the substrate. Moreover, by appropriately selecting the dopant dose, i.e., the number of ions per unit area of the ion beam impinging on a substrate, comparably high concentrations of atoms may be incorporated into a substrate as compared to other doping techniques, such as diffusion. In the case of an illustrative transistor, ion implantation may be used to form various doped regions, such as halo implant regions, extension implant regions and deep source/drain implant regions, etc.
As device dimensions are continually reduced, it is important that the depth of the source/drain regions for a transistor be shallow and that the implanted dopants are, to the extent possible, fully activated. Thus, heating processes such as a flash anneal or a laser anneal are performed for a very short duration to limit the diffusion of the implanted ions, so as to maintain the desired shallow dopant profile, while at the same time maximizing dopant activation. In general, the higher the annealing temperature is the greater the extent of dopant activation will be. However, the millisecond anneal times performed to activate shallow implant regions are insufficient to cure all of the damage to the substrate resulting from the ion implantation processes. Further, processes for maximizing dopant activation in certain implant regions may deactivate or otherwise damage dopants in other implant regions.
Accordingly, it is desirable to provide methods for fabricating integrated circuits with improved implantation processes. Furthermore, other desirable features and characteristics will become apparent from the subsequent detailed description and the appended claims, taken in conjunction with the accompanying drawings and the foregoing technical field and background.